Multiprocessor computer systems include multi-threaded processors in which a single physical processor is segmented into multiple logical processors, and multicore processors in which multiple processor cores are present in a single package or multiple packages.
Mobile computers such as notebook personal computers (PCs) typically incorporate certain power management techniques. One such technique is an adaptive technology that provides for changing both the operating voltage and frequency of the processor such that transition to a lower frequency (e.g., performance) point leads to a cubic reduction in power consumption by the processor at the lower frequency point.
Some mobile computers include processors that have performance states (P-state) that are controlled through operating systems. A processor may be able to operate in multiple P-states, with each varying in performance as well as varying in the amount of power consumption. Some current operating systems use this technique so that the processor is placed at an operating frequency that matches the processor utilization. For example, if the processor is idle 50% of the time, then the operating system places the processor at a frequency that is 50% of the maximum operating frequency.
FIG. 1 is a flow diagram illustrating a typical process for setting a P-state of a processor. The process 100 of FIG. 1 may be performed by an operating system (OS) during an idle time. Referring to FIG. 1, at block 101, the OS enters an idle loop. At block 102, the OS computes a busy ratio of the processor. At block 103, the OS re-computes a target P-state based on the computed busy ratio and the current performance of the processor. At block 104, the OS signals new target P-state to be set in the processor. Thereafter, at block 105, the OS exits the idle loop and executes the applications while the processor transitions into the new target P-state at block 106.
In a multiprocessor system, the OS typically computes the target P-state for each processor independently of the others. However, controlling P-states in multiprocessor systems can have a negative effect when multiple processor cores, logical or otherwise, are on the same integrated circuit and their P-states are being controlled independently. This is because the OS does not consider the effects of it's selection of the P-state for one processor upon other processors in the system when specifying the frequency and/or voltage changes applied to one processor and those changes would be applied to one or more other processors on the chip. For example, the OS could determine a first logical processor should be in a P-state with a lower performance than the P-state of a second logical processor on the same chip. This causes the chip as a whole to transition to a lower performance state and the second logical processor performance be forced to operate in the P-state below the performance level in which it is operating.